1. Field of the Invention
This invention relates to methods for the fabrication of dielectric layers employed within microelectronics fabrications. More particularly, the invention relates to methods for the formation of dielectric layers for inter-level separation of patterned conductor layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers.
As the level of integration of microelectronics devices has increased and the dimensions of microelectronics devices have decreased, the spacing between adjacent conductor layers has correspondingly decreased, and the separation between adjacent conductor lines within a patterned conductor layer has also diminished. It is desirable to form a dielectric layer over and around the conductor lines and between successive patterned conductor layers uniformly without voids or other defects.
The increased density of circuit per unit area of substrate has also created a need for greater complexity and density of interconnections between components and circuits. This has necessitated the use of multiple levels of interconnection layers, requiring that the dielectric layers separating levels of interconnection layers be fabricated with flat, smooth upper surfaces to permit formation of closely spaced conductor line patterns upon the underlying dielectric layer surfaces by conventional photolithographic methods which have very limited depth of focus for pattern image formation.
Of the methods and materials which may be employed to form dielectric layers disposed between and around the patterns and lines of patterned microelectronics conductor layers, silicon containing dielectric materials including but not limited to silicon oxide dielectric materials, silicon nitride dielectric materials and silicon oxynitride dielectric materials formed by methods including but not limited to sub-atmospheric pressure thermal chemical vapor deposition (SACVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) sputtering, reactive sputtering and spin-on-glass (SOG) methods have been found to be satisfactory. In particular, the filling in of narrow gaps within the conductor layers is especially well accomplished by employing gap filling layers of silicon oxide formed by SACVD methods employing ozone (O.sub.3) gas and tetra-ethyl-ortho-silicate (TEOS) vapor.
The employment of gap filling silicon oxide materials for forming dielectric layers between and around patterned conductor layers is not without problems, particularly as the separations between conductor lines become smaller. A narrow gap between lines tends to be covered over at the top before all of the inner region is filled, leaving a void or "keyhole" in the interior of the dielectric material otherwise filling the gap. The presence of voids in the dielectric layer is not necessarily undesirable per se from the standpoint of the dielectric constant of the dielectric layer, but such voids are essentially structural defects in the dielectric layer. These void defects would result in a loss of the structural integrity and the chemical inertness of the dielectric layer. These void defects are particularly undesirable if formation of a flat, smooth upper surface of the dielectric layer for subsequent conductor line pattern formation is accomplished by, for example, chemical mechanical polish (CMP) planarization. The method of CMP planarization, which is commonly employed for this purpose, would be likely to uncover such voids and produce an irregular and defective surface.
It is therefore towards the goal of providing improved methods for forming gap filling dielectric layers within microelectronics fabrications that the present invention is generally and more specifically directed.
Various methods have been disclosed to form dielectric layers suitable for inter level metal dielectric (IMD) layers within microelectronics fabrications.
For example, Andideh et al., in U.S. Pat. No. 5,270,264, disclose a method for filling narrow, high aspect ration gaps between conductor lines with a high quality inter-level metal dielectric material. The method employs a first dielectric layer deposited over and around adjacent conductors, followed by sputtering in a rare gas plasma to re-deposit dielectric material within and alongside the gap between the conductor lines, and then filling the gap with a second dielectric layer formed employing chemical vapor deposition (CVD) of silicon dioxide.
Further, Blalock et al., in U.S. Pat. No. 5,416,048, disclose a method for forming conductor lines with improved edge step coverage by a dielectric layer subsequently deposited over the conductor line. The method forms sloped profiles of conductor line edges by preferential sputter etching and oxidizing the conductor line material causing it to re-deposit along the sides of the conductor line and on the underlying substrate.
Still further, Ravi et al., in U.S. Pat. No. 5,661,093, disclose a method for increasing the moisture resistance of an interlevel dielectric layer of silicon oxide containing a halogen by minimizing halogen outgassing. The layer is formed by successive deposition of silicon oxide with halogen or other dopants to build up the desired final layer thickness.
Yet still further, Wang et al., in U.S. Pat. No. 5,679,606, disclose a method for forming a thick planar inter-level dielectric layer over metal conductor lines. The method employs an electron cyclotron resonance (ECR) process to deposit a silicon containing dielectric layer over aluminum-copper conductor lines, followed by deposition of a gap filling dielectric layer including argon gas flow and radiofrequency power to insure gap filling and enhanced planarization. The process may be repeated to achieve the final desired thickness. Finally, a capping layer is deposited to complete the gap filling and achieve the desired planarization.
Finally, Fulford Jr. et al., in U.S. Pat. No. 5,759,913, disclose a method for forming between interconnect lines, a dielectric layer having air gaps within its structure between the interconnect lines. The air gaps form due to the outgassing of a hygroscopic material layer, previously formed at the bottom of the separation between the interconnect lines, during the deposition of the dielectric layer between and around the interconnect lines, favoring the deposition of dielectric material along the sides of the lines. To complete the covering of the air gap thus formed, the deposition temperature is decreased to decrease the outgassing, allowing the dielectric layer to cover over the separation between the interconnect lines.
Desirable within the art are additional methods which may be employed for forming void-free dielectric layers for inter-level separation of conductor layers within a microelectronics fabrication. More particularly desirable in the art of integrated circuit microelectronics fabrication are additional methods for forming void-free dielectric layers to fill narrow gaps between closely spaced conductor lines and to separate patterned conductor levels while allowing formation of planarized surfaces of the dielectric layers.
It is towards the foregoing goals that the present invention is both generally and more specifically directed.